Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:12.1 (WebPack) - M.53d Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s500e
Project ID (random number) fd7c964f097b4564a5b58f0543d8f8e8.E6CE16B1204D46C39A9B2EC1D6D97869.8 Target Package: fg320
Registration ID __0_0_0 Target Speed: -5
Date Generated 2010-12-23T10:58:37 Tool Flow ISE
 
User Environment
OS Name Microsoft OS Release major release (build 7600)
CPU Name AMD Athlon(tm) 64 X2 Dual-Core Processor TK-57 CPU Speed 1900 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=12
  • AGG_IO=12
  • AGG_SLICE=2
  • NUM_4_INPUT_LUT=3
  • NUM_BONDED_IBUF=4
  • NUM_BONDED_IOB=8
  • NUM_SLICEL=2
NetStatistics
  • NumNets_Active=19
  • NumNets_Gnd=1
  • NumNodesOfType_Active_DOUBLE=25
  • NumNodesOfType_Active_DUMMY=12
  • NumNodesOfType_Active_DUMMYESC=4
  • NumNodesOfType_Active_HFULLHEX=1
  • NumNodesOfType_Active_HUNIHEX=1
  • NumNodesOfType_Active_INPUT=17
  • NumNodesOfType_Active_IOBOUTPUT=4
  • NumNodesOfType_Active_OUTPUT=3
  • NumNodesOfType_Active_PREBXBY=2
  • NumNodesOfType_Active_VFULLHEX=3
  • NumNodesOfType_Active_VLONG=1
  • NumNodesOfType_Active_VUNIHEX=11
  • NumNodesOfType_Gnd_INPUT=3
  • NumNodesOfType_Gnd_OMUX=3
  • NumNodesOfType_Gnd_OUTPUT=3
SiteStatistics
  • IOB-DIFFM=4
  • IOB-DIFFS=4
  • SLICEL-SLICEM=1
SiteSummary
  • IBUF=4
  • IBUF_INBUF=4
  • IBUF_PAD=4
  • IOB=8
  • IOB_OUTBUF=8
  • IOB_PAD=8
  • SLICEL=2
  • SLICEL_F=1
  • SLICEL_G=2
 
Configuration Data
IBUF_INBUF
  • IBUF_DELAY_VALUE=[DLY0:4]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:4]
  • PULL=[PULLUP:4]
IOB
  • O1=[O1_INV:0] [O1:8]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:8]
IOB_PAD
  • DRIVEATTRBOX=[12:8]
  • IOATTRBOX=[LVCMOS25:8]
  • SLEW=[SLOW:8]
 
Pin Data
IBUF
  • I=4
  • PAD=4
IBUF_INBUF
  • IN=4
  • OUT=4
IBUF_PAD
  • PAD=4
IOB
  • O1=8
  • PAD=8
IOB_OUTBUF
  • IN=8
  • OUT=8
IOB_PAD
  • PAD=8
SLICEL
  • F1=1
  • F2=1
  • F3=1
  • F4=1
  • G1=2
  • G2=2
  • G3=2
  • G4=2
  • X=1
  • Y=2
SLICEL_F
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • D=1
SLICEL_G
  • A1=2
  • A2=2
  • A3=2
  • A4=2
  • D=2
 
Tool Usage
Command Line History
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
bitgen 13 13 0 0 0 0 0
map 14 11 0 0 0 0 0
ngc2edif 4 4 0 0 0 0 0
ngdbuild 18 18 0 0 0 0 0
par 11 10 1 0 0 0 0
trce 10 10 0 0 0 0 0
xst 89 89 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/ise_c_overview.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/shem_shem_sch_tb PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=Schematic
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2010-12-07T10:51:34 PROP_intWbtProjectID=E6CE16B1204D46C39A9B2EC1D6D97869
PROP_intWbtProjectIteration=8 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_selectedSimRootSourceNode_behav=work.shem_shem_sch_tb PROP_AutoTop=true
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s500e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=fg320
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-5
PROP_PreferredLanguage=Verilog FILE_SCHEMATIC=1
FILE_UCF=1 FILE_VERILOG=2
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=4 NGDBUILD_NUM_LUT4=3 NGDBUILD_NUM_OBUF=8
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=4 NGDBUILD_NUM_LUT4=3 NGDBUILD_NUM_OBUF=8
NGDBUILD_NUM_PULLUP=4
 
ISim Statistics
Xilinx HDL Libraries Used=unisims_ver
Fuse Resource Usage=233 ms, 17084 KB
Total Signals=61
Total Nets=44
Total Blocks=17
Total Processes=46
Total Simulation Time=2 us
Simulation Resource Usage=0.0624 sec, 472154 KB
Simulation Mode=gui
Hardware CoSim=0