shem Project Status (12/23/2010 - 10:58:46) | |||
Project File: | chast1pros.xise | Parser Errors: | No Errors |
Module Name: | shem | Implementation State: | Programming File Generated |
Target Device: | xc3s500e-5fg320 |
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No Errors |
Product Version: | ISE 12.1 |
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36 Warnings (0 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of 4 input LUTs | 3 | 9,312 | 1% | ||
Number of occupied Slices | 2 | 4,656 | 1% | ||
Number of Slices containing only related logic | 2 | 2 | 100% | ||
Number of Slices containing unrelated logic | 0 | 2 | 0% | ||
Total Number of 4 input LUTs | 3 | 9,312 | 1% | ||
Number of bonded IOBs | 12 | 232 | 5% | ||
Average Fanout of Non-Clock Nets | 2.43 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | طْ 23. لمي 10:56:42 2010 | 0 | 36 Warnings (0 new) | 0 | |
Translation Report | Current | طْ 23. لمي 10:57:20 2010 | 0 | 0 | 0 | |
Map Report | Current | طْ 23. لمي 10:57:44 2010 | 0 | 0 | 2 Infos (0 new) | |
Place and Route Report | Current | طْ 23. لمي 10:58:14 2010 | 0 | 0 | 1 Info (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | طْ 23. لمي 10:58:22 2010 | 0 | 0 | 5 Infos (0 new) | |
Bitgen Report | Current | طْ 23. لمي 10:58:36 2010 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | رِ 22. لمي 22:15:50 2010 | |
WebTalk Report | Current | طْ 23. لمي 10:58:38 2010 | |
WebTalk Log File | Current | طْ 23. لمي 10:58:46 2010 |