shem Project Status (12/23/2010 - 10:58:46)
Project File: chast1pros.xise Parser Errors: No Errors
Module Name: shem Implementation State: Programming File Generated
Target Device: xc3s500e-5fg320
  • Errors:
No Errors
Product Version:ISE 12.1
  • Warnings:
36 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 3 9,312 1%  
Number of occupied Slices 2 4,656 1%  
    Number of Slices containing only related logic 2 2 100%  
    Number of Slices containing unrelated logic 0 2 0%  
Total Number of 4 input LUTs 3 9,312 1%  
Number of bonded IOBs 12 232 5%  
Average Fanout of Non-Clock Nets 2.43      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentطْ 23. لمي 10:56:42 2010036 Warnings (0 new)0
Translation ReportCurrentطْ 23. لمي 10:57:20 2010000
Map ReportCurrentطْ 23. لمي 10:57:44 2010002 Infos (0 new)
Place and Route ReportCurrentطْ 23. لمي 10:58:14 2010001 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentطْ 23. لمي 10:58:22 2010005 Infos (0 new)
Bitgen ReportCurrentطْ 23. لمي 10:58:36 2010000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Dateرِ 22. لمي 22:15:50 2010
WebTalk ReportCurrentطْ 23. لمي 10:58:38 2010
WebTalk Log FileCurrentطْ 23. لمي 10:58:46 2010

Date Generated: 12/23/2010 - 10:58:47